FINFETs feature a thin body, or FIN, of silicon (Si) formed on a bulk Si or silicon-on-insulator (SOI) substrate and controlled by two gates or surrounded by a gate. With such a design, the body is well controlled and short channel effect is suppressed. As a result, FINFETs are suitable for device dimension scaling and are regarded as a vertical or three-dimensional solution to replace planar metal oxide semiconductor field effect transistors (MOSFETs). Indeed, FINFETs are regarded as the structural solution for sub-22 nm technology because of their scalability and gate control.
High voltage devices are required in integrated circuits for liquid crystal display (LCD) driver applications and power management applications. However, FINFETs are typically used for low voltage and/or low power applications. Risks for high voltage applications include drain endurance, device reliability, and gate-induced drain leakage. Unlike planar laterally diffused metal oxide semiconductor (LDMOS) devices that may have improved voltage endurance and reliability by including a shallow trench isolation (STI) region in the drift region, it is difficult to introduce STI structures into FINFETs because of the thin FIN. As a result, a high electric field region exists at the gate edge for high voltage applications, which becomes the weak point of the FINFET structure. While the gate stack region may be optimized to reduce the gate field and increase reliability, issues still exist. Thus, it would be beneficial to extend the high voltage capability to FINFET devices and process design to integrate high voltage and standard voltage circuitry in the same system and manufacturing process.
A need therefore exists for methodology enabling formation of FINFETs suitable for high voltage/high power applications and the resulting devices.